As integrated circuit technology has advanced, the complexity and density of circuit devices that are formed within a single integrated circuit (IC) has increased dramatically. Consequently, several problems have arisen with regard to testing such integrated circuits. For example, while the methodology for testing a memory array may be relatively straight forward, memory array chips typically have far fewer input/output (I/O) pins available to an IC tester than are required to adequately test the memory array. A general solution to this problem is to imbed test circuitry on the chip itself. Such testing facilities are frequently referred to as built-in-self-test (BIST), array self-test (AST), or array built-in self-test (ABIST) circuits and will hereinafter be referred to generically as BIST circuits.
A conventional testing apparatus for an IC memory includes a BIST circuit and at least one memory array that are coupled to an integrated circuit tester. According to the conventional BIST testing methodology, the IC tester scans data into the BIST circuit in order to initialize a number of state machine latches therein. Subsequently and in response to a clock signal, the BIST circuit applies internally generated test data and address data to the memory array and then compares the data that is read from the memory array with a set of expected data. In response to a discrepancy between the output data and the expected data, the BIST circuit indicates that a failure within memory array has been detected by generating a diagnostic fail signal. In response, the IC tester records the cycle the fail signal was asserted. Utilizing an algorithm, the IC tester calculates the cycle in which the failure actually occurred and reinitializes the BIST circuit. Thereafter, the BIST circuit is executed again to the cycle in which the failure occurred by applying clock signals for an appropriate number of cycles. The state machine data at the failing cycle is then scanned out by the IC tester and utilized to generate a bit-fail map for use in failure analysis.
One shortcoming of the conventional BIST testing methodology is the inability of the IC tester to test the memory array at typical operating speeds, e.g., above 200 megahertz (MHz), of fast memories. Operating at or above 200 MHz necessitates that the IC tester monitor the diagnostic fail signal at least every 5 nanoseconds (ns) in order to capture the cycle in which the failure of interest occurs. However, because of I/O gate delays and signal propagation delays, the feedback provided by the diagnostic fail signal is too slow to indicate the cycle in which the failure of interest occurs and then stop the BIST state machine in the very same clock cycle that generated the failure information. More specifically, present BIST solutions are unable to capture fail data for diagnostics and mapping at a high performance speed at which the memory under test is able to run. Consequently, ambiguity of the fails results because the BIST circuit is several clock cycles ahead of the diagnostic fail signal. As a result, the address and data information is no longer present at the time that the diagnostic fail signal occurs. Methods are available in order to pipeline the data and address information and retain the data until the diagnostic fail signal is generated. However, this results in more dedicated circuitry for test diagnostics, which consumes valuable chip area.
For these reasons, a need exists for a system for and method of performing high speed memory diagnostics via BIST, in order to perform memory diagnostics at full operating speed and in order to avoid implementing significant additional diagnostic circuitry on the integrated circuit device.